Qualify Simulation Test Sequence with Formal Method
Date Issued
2009
Date
2009
Author(s)
Liu, Ji-Han
Abstract
Due to the increasing design complexity, verification of modern VLSI designs has become an essential work in the design flow. Simulation is predominant verification method to verify the functionality of gate level or register-transfer level (RTL) design nowadays. However, it lacks one quantitative metric with enough discrimination to verify the simulation completeness although there exist several coverage metrics for qualifying the test sequence manually defined or randomly generated in simulation. Accordingly, sequential depth computation and reachability analysis of the formal verification techniques are employed to derive or infer the feasible metrics for measuring the quality of test sequence and coverage of simulation. Hence, a modified version of the mentioned metric is proposed to overcome the problem of failure in sequential depth computation and BDD (binary decision diagrams) of transition relationship construction due to the system resource explosion. The proposed metrics consist of the requirements of simulation correctness of sequential depth, simulation completeness of states or cubes of Boolean state space in limited simulation timeframe, simulation performance of sequential depth and weighting in accordance with designer’s preference or concern of the simulation.
Subjects
Simulation
Formal Verification
BDD (Binary Decision Diagrams)
coverage metric
sequential depth
reachability analysis
Type
thesis
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