Hierarchical model order reduction for signal-integrity driven interconnect synthesis
Journal
Great Lakes Symposium on VLSI (GLSVLSI)
Date Issued
2001-01
Author(s)
Yu-min Lee
Abstract
Article Share on Hierarchical model order reduction for signal-integrity interconnect synthesis Authors: Yu-Min Lee Department of Electrical and Computer Engineering, University of Wisconsin at Madison, Madison, WI Department of Electrical and Computer Engineering, University of Wisconsin at Madison, Madison, WIView Profile , Charlie Chung-Ping Chen Department of Electrical and Computer Engineering, University of Wisconsin at Madison, Madison, WI Department of Electrical and Computer Engineering, University of Wisconsin at Madison, Madison, WIView Profile Authors Info & Claims GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSIMarch 2001Pages 109–114https://doi.org/10.1145/368122.368883Published:01 March 2001Publication History 3citation178DownloadsMetricsTotal Citations3Total Downloads178Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Publisher SiteGet Access
Type
conference paper