Exploring Synchronous Page Fault Handling
Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal Volume
41
Journal Issue
11
Pages
3791
Date Issued
2022-11-01
Author(s)
Abstract
The advance of nonvolatile memory in storage technology has presented challenges in redefining the ways in handling the main memory and the storage. This work is motivated by the strong demands in effective handling of page faults over ultralow-latency storage devices. In particular, we propose synchronous and asynchronous prefetching strategies to satisfy process executions with different memory demands in supporting of synchronous page fault handling. An adaptive CPU scheduling strategy is also proposed to cope with the needs of processes in maintaining their working sets in the main memory. Six representative benchmarks and applications were evaluated. It was shown that our strategy can effectively save 12.33% of the total execution time and reduce 13.33% of page faults, compared to the conventional demand paging strategy with nearly no sacrificing of process fairness.
Subjects
Context switch | data prefetching | killer microsecond | page faults | process scheduler | synchronous I/O completion designs | ultralow-latency (ULL) devices
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Type
journal article