DR-scan: A Test Methodology for Dual-rail Asynchronous Circuits

This thesis presents a test methodology, Dual-rail scan (DR-scan), for dual-rail asynchronous circuits. We propose a full-scan design for testability (DfT) technique, which uses all four codewords in dual-rail logic so that scan chains can be shifted without clock. Our DfT can be applied to various implementations, including delay insensitive minterm synthesis (DIMS), null conventional logic (NCL), and pre-charge half buffer (PCHB). DR-scan enables traditional full-scan automatic test pattern generation (ATPG) to generate high fault coverage test patterns. Experimental results show area overhead of 16-bit multiplier linear pipeline is only 9%. Fault coverage on non-linear pipeline circuits are higher than 98%.