The system implementation of I-phone hardware by using low bit rate speech coding
Resource
Signal Processing Systems, 1997. SIPS 97 - Design and Implementation., 1997 IEEE Workshop on
Journal
Signal Processing Systems, SIPS 97
Pages
-
Date Issued
1997-11
Date
1997-11
Author(s)
DOI
N/A
Abstract
This paper presents a system implementation for Internet-phone communication with real-time speech coding schemes. A low-cost speech processing coprocessor is embedded. A CPLD device is used to implement the interface between the host processor and the coprocessor via conventional parallel port. At the headphone interface, there are a 16-bits PCM CODEC and an audio amplifier with acoustic echo cancellation features employed. The system consists of a mixed implementation of software and hardware. The experimental coding rate is 8.5 kbps. In such rate, a 14.4 kbps or higher speed modem can conform to offer full-duplex speech for the applications such as digital simultaneous voice data (DSVD).
SDGs
Type
journal article
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