Design of High-Speed and Low-Power Analog-to-Digital Converters
Date Issued
2016
Date
2016
Author(s)
Lin, Chin-Yu
Abstract
Analog-to-digital converter (ADC) has been recognized as one of the crucial building blocks in the modern SoC system because it provides the link between the real-world analog information and the digital signal processors (DSPs). The demand on high-speed and low-power ADCs has increased as many portable applications grow rapidly in recent years. In this dissertation, two ADCs are presented to achieve high-speed and low-power design. The first part of this dissertation demonstrates a 12-b, 210-MS/s 2-channel interleaved pipelined-SAR ADC. The proposed ADC is partitioned into 3 stages with passive residue transfer technique between the 1st and the 2nd stages for power saving and active residue amplification between the 2nd and the 3rd stages. The prototype, fabricated in a 65-nm CMOS technology, consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.5 dB at DC and 60.1 dB near Nyquist-rate. The second part present a 10-b, 2.6-GS/s time-interleaved SAR ADC for the RF front-end of the next-generation mobile system. A 16-channel time-interleaved 10-b SAR ADC, employing the proposed delta-sampling auxiliary SAR ADC and digital mixing calibration to correct timing skew error, achieves a 2.6-GS/s sampling rate. The ADC has been fabricated in a 40-nm CMOS technology and achieves a 50.6-dB SNDR at Nyquist rate while dissipating 18.4 mW from a 1.1-V power supply.
Subjects
Pipelined-SAR ADC
Time-Interleaved ADC
timing skew calibration
Type
thesis
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