Static Noise Margin Analysis for Cryo-CMOS SRAM Cell
Journal
2021 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2021
Date Issued
2021
Author(s)
Liu C.-J.
Abstract
In this work, we analyzed the static noise margin (SNM) of cryo-CMOS SRAM cells operated at superthreshold (Vdd = 0.75 V) and subthreshold (Vdd = 0.2 V) regions. The impact of the temperature and write-assist (WA) technique on the ultra-thin-body (UTB) SOI SRAM cell has been examined. UTB SOI MOSFET at 77K shows a steep subthreshold slope and reduced leakage, which enables the UTB SOI SRAM cell to operate at low Vdd. Our results show that at Vdd = 0.2V, compared to 300K, UTB SOI SRAM with WA at 77K shows 39.6%, 32.2%, and 11% improvements in read, hold, and write SNM, respectively. Therefore, cryo-CMOS SRAM enabling low Vdd operation and improving stability is a highly promising solution to improve both performance and power efficiency. ? 2021 IEEE.
Subjects
Cryo-CMOS
cryogenic
SRAM
static noise margin
subthreshold operation
write-assist technique
Cells
CMOS integrated circuits
Cytology
Margin analysis
SOI-MOSFETs
SRAM Cell
Static noise margin
Subthreshold
Subthreshold operation
Subthreshold slope
Ultrathin body
Write-assist technique
Static random access storage
SDGs
Type
conference paper