Advanced Visual Chip Design for Feature Extraction and Its Application
Date Issued
2007
Date
2007
Author(s)
Lu, Chieh-Lun
DOI
en-US
Abstract
Recently, in advanced robotic system, image information has been an important sense to recognize the environment, and researchers can realize specific or complicated applications by combining several single image operations to form up an advanced multi-layer image processing. However, limited by the CPU-based architecture, multi-layer image processing is always implemented in software system which may cause serious time-delay or resource grabbing. Consequently, it will probably lead to failure of executing other tasks in robotic system. In this thesis, after deeply analyzing the data flow and operations in multi-layer image processing, we can find out that it has many parallel and pipeline properties inherently, and these properties actually are suitable to implement in hardware system. Therefore, we design a novel hardware architecture, which not only accomplish the multi-layer image processing on a chip independently, but also achieve real-time performance.
By this hardware architecture, we realize the multi-scale Harris corner detector in FPGA and use the software-hardware co-design to implement the overall pattern recognition process. Since the features are detected by our visual chip in real-time, we combine it with Shape Context descriptor and TPS(Thin Plate Spline) transformation realized in software system to do the pattern recognition, even though there are scale、rotational variances, and furthermore the nonlinear deformation of the object, our system can track it very well and in real-time.
Subjects
多階層影像處理
平行與管線特性
多重尺度Harris角點
軟硬體共同設計
目標物辨識
Multi-layer Image Processing
Parallel and Pipeline Properties
Multi-scale Harris corner
software-hardware co-design
Pattern Recognition
Type
thesis