An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique
Journal
IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Volume
63
Journal Issue
5
Pages
683--692
Date Issued
2016-05
Author(s)
Abstract
An 8 b 700 MS/s 1 b/cycle asynchronous successive approximation register (SAR) analog to digital converter (ADC) which skips comparator metastability is presented. A delay-shift technique is proposed to shift the delay of comparator to generate a 1.5 b redundancy range and to accelerate comparison speed. This reduces the settling requirement and compensates for the dynamic offset by redundancy. The prototype ADC in 40 nm CMOS technology achieves an SNDR of 43.9 dB at Nyquist rate and consumes 5 mW with a 1.2 V supply. This results in an FoM of 56 fJ/conversion-step. Due to no extra calibration circuit, the core circuit occupies an area of only 0.006 mm2. © 2004-2012 IEEE.
Subjects
Energy efficiency; high speed; metastability; redundancy; SAR ADC
SDGs
Other Subjects
Comparator circuits; Comparators (optical); Energy efficiency; Redundancy; Calibration circuits; CMOS technology; High Speed; Metastabilities; Nyquist rate; SAR ADC; Shift technique; Successive approximation register analogto-digital converters (ADC); Analog to digital conversion
Type
journal article