Design and Implementation of Delay Locked Loop Clock Generator
Date Issued
2009
Date
2009
Author(s)
Wen, Kuo-Chih
Abstract
PLLs is have been widely used for clock generation. DLL also can be used for clock generation. DLL-based clock multipliers have several inherent advantages over conventional PLL-based clock multipliers. The DLL is a first-order system and has no jitter accumulation. owever, conventional DLL-based clock generator cannot operate in high speed operation frequency except using inductance. In this thesis, a new type edge combiner is proposed. A new type edge combiner can operate up to 7.5G without inductance using TSMC 0.13um CMOS process. Besides, we modified a conventional startup circuit to solve its timing problem in high speed operation frequency.
Subjects
DLL
startup
edge combiner
Type
thesis
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ntu-98-R95943113-1.pdf
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