A 132.6-GHz phase-locked loop in 65 nm digital CMOS
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
58
Journal Issue
10
Pages
617-621
Date Issued
2011
Author(s)
Lin, B.-Y.
Abstract
A phase-locked loop (PLL) with the proposed voltage-controlled oscillator (VCO) and a divide-by-2 injection-locked frequency divider (ILFD) is fabricated in 65-nm digital CMOS technology. The proposed VCO and the divide-by-two ILFD operate at the higher and lower poles, respectively, of two fourth-order LC ladders. The frequency ratio between the VCO and its first divide-by-2 ILFD is kept by scaling the inductances and the capacitances. The design considerations of this VCO and the locking range of this ILFD are discussed. The measured locking range of this PLL is 132.1-132.6 GHz. It consumes 120.8 mW from 1.35-V supply, excluding the output buffers. The chip area is 0.96 × 0.92 mm 2. © 2011 IEEE.
Subjects
Fourth-order LC ladder; injection-locked frequency divider (ILFD); phase-locked loop (PLL); voltage-controlled oscillator (VCO)
SDGs
Other Subjects
Capacitance; Circuit oscillations; CMOS integrated circuits; Ladders; Oscillistors; Phase locked loops; Variable frequency oscillators; Voltage dividers; Design considerations; Digital CMOS technology; Frequency ratios; Injection Locked Frequency Divider(ILFD); LC ladders; Locking range; Output Buffer; Phase Locked Loop (PLL); Frequency dividing circuits
Type
journal article