A Low power Network-on-Chip Architecture Based on Low Switching Method
Date Issued
2007
Date
2007
Author(s)
Huang, Hung-Yun
DOI
en-US
Abstract
The design of the Low power VLSI circuit is one of the most important issues at the present time technology. In the SoC (System-on-Chip), with ever increasing complexity of VLSI design and IP cores, the inter-communication between IP cores becomes the noteworthy challenge. In order to solve the problem of the data communication, the Network-on-Chip is proposed to deal with the difficulties of inter-communication between IP cores. In the NoC, the main components are Switch (or so-called Router) and Network Interface (NI, or so-called Wrapper). In this thesis, we propose a low-switching network interface used in the 2D mesh topology and the bus-invert method, we can accomplish the goal of the low power for recoding the data. According to the experimental results, with the method mentioned in this thesis, the power consumption can be saved about 20% on average when the percentage of the inter-connection power in the total power is 80%. In this work, we can effectively reduce the switching activity of the data transfer to save the power consumption of the NoC data-communication.
Subjects
晶片網路
低功率
晶片系統
網路介面
匯流排反向
Network-on-Chip
Low power
System-on-Chip
Network Interface
Bus-invert
Type
thesis
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