Analysis and VLSI Architecture Design of Scalable Video Coding Encoder and Decoder
Date Issued
2010
Date
2010
Author(s)
Chuang, Tzu-Der
Abstract
With advances in video coding technology, the demand of high quality, high definition, and scalable functionality of video encourages the developments of newest video coding standards — H.264/AVC scalable extension, the scalable video coding (SVC). In this dissertation, we aim to build a Full HD SVC/H.264 High Profile video encoder and a SVC/MVC/H.264 Quad Full HD video decoder. We classify this dissertation into three part, SVC coding tools, high definition video encoder, and high definition video decoder. In each part, the discussion includes algorithm design, system-level architecture design, and module-level architecture design for memory bandwidth, computation complexity, hardware cost, and power consumption issues.
In the first part, the analysis and architecture design of the scalability coding tools are presented. For the temporal scalability, the data independency of the hierarchical B-frame is utilized to improve the level of data reuse from MB level to frame level. For the spatial scalability, the data flow and the impact of the inter-layer prediction are analyzed. In SVC encoder, low complexity and low cost FME algorithm and architecture with supporting SVC inter-layer prediction is described. In SVC decoder, we propose the MB-level on-the-fly padding and on-line upsampling which convert the frame-level resampling operation into MB-level processes. 34% of decoding bandwidth and 36% of extra processing cycles are reduced. Considering the characteristic of the temporal and spatial scalabilities, an adaptive spatial-temporal hierarchical ME with reconfigurable architecture is contributed to support the diverse coding configurations. For the quality scalability, the FGS, MGS and CGS are discussed. Three design techniques, the scan bucket preprocessing, early context modeling and first scan pre-encoding are proposed to eliminate the irregular frame-level access of FGS and reduce 92% of memory bandwidth. For CGS and MGS decoding, we propose the layer-interleaving decoding scheme which reduces 51% and 41% of total decoding bandwidth compared with the typical layer-by-layer decoding scheme.
In the second part, we focus on the implementation of a HD 1080p H.264 High Profile and SVC video encoder. A hardware oriented high throughput intra prediction algorithm and VLSI architecture are provided. Then, we integrate all the proposed hardware architectures of SVC and High Profile coding tools into a single chip video encoder. Two-level design techniques are provided. On the system level, the frame-parallel encoding structure and the frame-level data reuse scheme for B-frame coding are proposed to reduce 25%~50% of memory bandwidth of ME. In addition, to support SVC quality scalability, the two-frame pipeline architecture is also proposed for frame-level FGS coding. On the module level, the proposed algorithms and architectures of scalable coding tools in the first part are implemented. These architectures achieve 70% and 90% of bandwidth reduction in IME and FGS, and 7.2X processing throughput in FME. This chip is implemented on a 16.76mm2 die with UMC 90nm process and dissipates 306/411mW at 120/166MHz for high profile and SVC encoding.
In the last part of dissertation, the processing throughput limitation of CABAD entropy decoding and the bandwidth requirement of motion compensation for Quad Full HD and multi-view video decoding are discussed. For entropy decoding, we propose a branch selection multi-symbol CABAD architecture which has 2.3~4.9X greater throughput than previous works. To reduce the bandwidth, we propose a two-way associative cache-based motion compensation architecture with the DRAM-friendly access strategy and low precharge/active data mapping. A total of 73% of motion compensation bandwidth is saved. At the end, a 59.5mW worldwide first single-chip high-performance, low-bandwidth, low power consumption Multi-standard video decoder for H.264/AVC High Profile, SVC High Profile, and MVC High Profile is presented. Two-level power reduction strategies are applied to reduce 47% of power consumption. Only 59.5mW is required for QFHD single view video decoding. With the ability to decode SVC, it supports spatial scalability from QCIF to 1080p HD, and quality scalability to provide various bitrate-quality-power decoding trade-off points. View scalability for 3D and multi-view applications is also provided with MVC decoding. The chip is implemented on an 8.53mm2 die with UMC 90nm CMOS. The proposed decoder can support applications from low-power portable devices to high-end QFHD and 3DTV.
Subjects
SVC
encoder
decoder
Type
thesis
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