A 2.5 GHz all-digital delay-locked loop in 0.13 mu m CMOS technology
Journal
Ieee Journal of Solid-State Circuits
Journal Volume
42
Journal Issue
11
Pages
2338-2347
Date Issued
2007
Author(s)
Yang, Rong-Jyi
Abstract
A 2.5 GHz, 30 mW, 0.03 mm 2 , all-digital delay-locked loop (ADDLL) in 0.13 mum CMOS technology is presented. The tri-state digital phase detector suppresses the dithering phenomenon and reduces the output peak-to-peak jitter for a counter-controlled digital DLL. The lattice delay unit has both a small delay step and a fixed intrinsic delay of two nand gates. A modified successive approximation register-controller reduces the locking time and allows the DLL to track the process, voltage, temperature, and load variations. This ADDLL locks in 24 cycles and has a closed-loop characteristic. The measured peak-to-peak jitter is 14 ps at 2.5 GHz.
SDGs
Type
journal article