A grouping heuristic algorithm for gate matrix layout
Resource
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Journal
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Pages
-
Date Issued
1989-05
Date
1989-05
Author(s)
Liu, Jongping
Lai, Feipei
DOI
N/A
Abstract
For the gate matrix layout problem, it is necessary to minimize the area of the layout and the total wire length. The authors propose grouping poly-gates as a pseudo gate to simplify the problem and reduce execution time. Good results have been obtained very quickly using the grouping insertion.>
Type
journal article
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