A Low-Power DRAM System with Thermal Control for Multi-Core Systems
Date Issued
2014
Date
2014
Author(s)
Lin, Chung-Hsiang
Abstract
DRAMs are used as the main memory in most computing systems today. However, memory system performance has been historically lagged behind CPU performance, and this problem exacerbates in a multi-core system since memory resources are shared by multiple cores on a chip. To sustain concurrent memory requests from multiple cores, the speed, bandwidth, and capacity of DRAM memories continue to increase. Studies show that DRAMs now consume a significant part of the overall system power, and the temperature of DRAMs is also approaching its limit. Therefore, the challenge that we are facing today from DRAM memory management is how to achieve desired DRAM power reduction, and meet the performance and thermal constraints at the same time. Since the background power of DRAMs usually consumes more than 50% of the total DRAM power, I focus on reducing DRAM background power with negligible performance overhead, and meeting the DRAM thermal constraint in this dissertation.
The background power of DRAMs is composed of power consumption of peripheral leakage which depends on DRAM power states and refresh power. To reduce the DRAM peripheral leakage, I propose a joint performance, power and thermal management framework (PPT) through orchestrating task execution and page allocation to exploit DRAM low-power modes efficiently. The PPT framework adapts to system loading to maximize peripheral leakage power savings and avoid memory thermal hotspot at the same time whiling sustaining the system bandwidth demand. For refresh power reduction, I propose SECRET (Selective Error Correction for Refresh Energy reducTion) that is designed to reduce the inevitable refresh processes by prolonging the refresh interval and correcting the retention errors by ECC (Error Correcting Code). The key observation I make is that retention errors can be treated as hard errors rather than soft errors, and only few DRAM cells have large leakage to cause retention errors. Therefore, instead of equipping error correction capability in all memory cells as existing ECC schemes, I only allocate error correction information to leaky cells under a refresh interval to minimize the overheads of ECC.
The architectural supports for these two techniques do not conflict, so they can be used at the same time. Since both techniques incur negligible performance degradation, adopting them together would only hurt performance slightly as well. The effectiveness for power reduction and thermal control of these two techniques used simultaneously is as good as that of these two techniques used separately, because they reduce different parts of the DRAM background power and there is no interference between these two methods. So, utilizing the PPT and SECRET frameworks can reduce both the peripheral leakage power and refresh power of DRAM systems and alleviate the operating temperature with negligible overheads in performance and hardware modifications.
Subjects
動態隨機存取記憶體
功率
溫度
週邊電路
刷新
SDGs
Type
thesis
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