Analysis of the Gate–Source/Drain Capacitance Behavior of a Narrow-Channel FD SOI NMOS Device Considering the 3-D Fringing Capacitances Using 3-D Simulation
Resource
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 10, OCTOBER 2006
Journal
IEEE Transactions on Electron Devices
Journal Volume
VOL. 53
Journal Issue
NO. 10
Pages
-
Date Issued
2006-10
Date
2006-10
Author(s)
DOI
246246/200611150121241
Abstract
This paper reports an analysis of the gate–source/
drain capacitance behavior of a narrow-channel fully depleted
(FD) silicon-on-insulator (SOI) NMOS device considering the
three-dimensional (3-D) fringing capacitances. Based on the 3-D
simulation results, when the width of the FD SOI NMOS device
is scaled down to 0.05 μm, the inner-sidewall-oxide fringing capacitance
(CFIS), due to the fringing electric field at the edge of
the mesa-isolated structure of the FD SOI NMOS device biased at
VG = 0.3 V and VD = 1 V, is the second largest contributor to
the gate–source capacitance (CGS). Thus, when using nanometer
CMOS devices with a channel width smaller than 0.1 μm, CFIS
cannot be overlooked for modeling gate–source/drain capacitance
(CGS/CGD).
Subjects
Capacitance
CMOSFETs
modeling
silicon-oninsulator
(SOI) technology, simulation
(SOI) technology, simulation
Publisher
Taipei:National Taiwan University Dept Elect Engn
Type
journal article
File(s)![Thumbnail Image]()
Loading...
Name
169.pdf
Size
803.72 KB
Format
Adobe PDF
Checksum
(MD5):3907c216af25cbb05a35f6b5ee9eb9ac