Automatic Partitioner for Distributed Parallel Verification Simulation
Date Issued
2008
Date
2008
Author(s)
Kang, Jeh-Yen
Abstract
Due to the increasing complexity of circuit design, the verification through simulation has become a bottleneck of the IC design process. Distributed parallel simulation seems to be one of the best ways to solve the problem. In order to distribute the workload of the simulation into multiple processes, the design has to be carefully partitioned first. Most previous technique had focused on gate level partition. At present, we work extends a previously implemented Verilog gate-level partitioner to support RTL and behavior level partitioning. This technique can be used for partitioning special information structure, such as global access, function calls and memory access which are described in this paper. The experimental results show that our techniques are capable of accelerating the speed of the simulation
Subjects
Distributed Simulation
Parallel Simulation
RTL Level Partitioner
Behavior Level Partitioner
Type
thesis
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