A 14b 20MSamples/s CMOS Pipelined ADC
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
36
Journal Issue
6
Pages
3355-3364
Date Issued
2001
Author(s)
Abstract
The capacitor error-averaging technique, updated with look-ahead decision and digital correction, is used to demonstrate a 14-b 20-Msamples/s pipelined analog-to digital converter (ADC) with no trimming or calibration. The prototype ADC exhibits a differential nonlinearity (DNL) of +0.23/-0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/-1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The prototype in 0.5-/spl mu/m CMOS occupies an area of 4.5/spl times/2.4 mm/sup 2/ and consumes 720 mW at 5 V.
SDGs
Type
journal article