Video encoder design for high-definition 3D video communication systems
Journal
IEEE Communications Magazine
Journal Volume
48
Journal Issue
4
Pages
76-86
Date Issued
2010
Author(s)
Tsung, P.-K.
Ding, L.-F.
Chen, W.-Y.
Chuang, T.-D.
Chen, Y.-H.
Hsiao, P.-H.
Chien, S.-Y.
Chen, L.-G.
Abstract
VLSI realization of video compression is the key to real-time high-definition 3D communication systems. The newly established multiview video coding standard, as an extension profile of H.264/AVC, draws more and more attention for its high compression ratio and free-viewpoint support. Besides providing the 3D experience, multiview video can also give users complete scene perception. However, the multiple-viewpoint throughput requirement of MVC increase the complexity and hardware cost dramatically. The system memory bandwidth, on-chip memory size, and processing data throughput of each module all need to be optimized in an MVC encoder. Therefore, efficient hardware solutions for MVC architecture design are needed. In this article an overview of 3D video coding standards developments and design challenges of an MVC encoder are discussed. Then the algorithm and architecture optimization schemes are proposed. For the trade-off between system memory bandwidth and on-chip memory size, a cache-based prediction engine is proposed to ease both design challenges. Moreover, the hybrid open-close loop intra prediction scheme and the frame-parallel pipeline-doubled dual CABAC solve the throughput requirement problem. At the end of this article, based on all the proposed solutions, a prototype single-chip MVC encoder design with processing ability of 4096 × 2160 single-view to 1280 × 720 seven-view is presented.
SDGs
Type
journal article