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  4. Experiences with Parallel N-Body Simulation.
 
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Experiences with Parallel N-Body Simulation.

Journal
Proceedings of the 6th Annual ACM Symposium on Parallel Algorithms and Architectures, SPAA 1994
Pages
122-131
Date Issued
1994
Author(s)
PANGFENG LIU  
Bhatt, Sandeep N.
DOI
10.1145/181014.181081
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/489388
https://www.scopus.com/inward/record.uri?eid=2-s2.0-84947725835&doi=10.1145%2f181014.181081&partnerID=40&md5=1578cc4275dcda83c765b13b57ab0c44
URL
https://doi.org/10.1145/181014.181081
Abstract
This paper describes our experiences developing high- performance code for astrophysical iV-body simulations. Recent N-body methods are based on an adaptive tree structure. The tree must be built and maintained across physically distributed memory; moreover, the communication requirements are irregular and adaptive. Together with the need to balance the computational work-load among processors, these issues pose interesting challenges and tradeoffs for high-performance implementation. Our implementation was guided by the need to keep solutions simple and general. We use a technique for implicitly representing a dynamic global tree across multiple processors which substantially reduces the programming complexity as well as the performance overheads of distributed memory architectures. The contributions include methods to vectorize the computation and minimize communication time which are theoretically and experimentally justified. The code has been tested by varying the number and distribution of bodies on different configurations of the Connection Machine CM-5. The overall performance on instances with 10 million bodies is typically over 30% of the peak machine rate. Preliminary timings compare favorably with other approaches. © 1994 ACM.
SDGs

[SDGs]SDG9

Other Subjects
Forestry; Parallel algorithms; Parallel architectures; Parallel processing systems; Trees (mathematics); Communication time; Computational work; Distributed Memory; Distributed memory architecture; High performance codes; High performance implementations; Multiple processors; Programming complexity; Memory architecture
Type
conference paper

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