Design and Implementation of High Speed Channel Equalizer
Date Issued
2005
Date
2005
Author(s)
Lo, Chi-Lun
DOI
en-US
Abstract
Because of popularization of the internet network in recent years, the transmitted data quantity is growing up with each passing day. Development of high speed wired-line communication system provides one of the best solutions for solving the data jam and promoting information popularization. When the operating frequency of the communication system is beyond gigahertz range, not only the design of the transceiver front-end circuits meets difficulties but the loss of the transmission channel is another problem. An equalizer circuit plays an important role in the transceiver circuits, which is used to compensate the channel loss due to electromagnetic effects.
This thesis describes the design and implementation of the high speed transmission channel equalizer circuit. First of all, we will discuss three different techniques to model the transmission line for the design of the equalizer circuit. Next, a design of high speed CMOS coaxial cable equalizer is presented. In order not to increase the chip area, we use active inductive peaking load to replace monolithic on-chip inductor for high frequency response. This circuit can reach a data rates up to 3.125Gbps. Finally, we present another circuit implementation of a high speed CMOS equalizer. This circuit is designed to receive data rate up to 10Gbps and compensate the broadband loss of the printed-circuit-board (PCB) trace. It incorporates an input stage for high frequency gain without DC power consumption and two cascaded active filter stages for the remained frequency loss of the PCB channel. Both of the circuit designs are implemented with a standard 0.18um CMOS process.
Subjects
傳輸通道
訊號補償
等化器
high speed wired-line communication system
transmission channel
siganl compensation
equalizer
Type
thesis
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