Analog Front-End Circuit Design for 10GBASE-T Ethernet
Date Issued
2007
Date
2007
Author(s)
Chuang, Kai-Hsiang
DOI
en-US
Abstract
Since the Internet expands rapidly, the data rate of the local area network reaches 10 Gb/s. The optical systems with the data rate of 10 Gb/s have been proposed and implemented a few years ago. However, for the cost point of view, it is desired to implement the system with data rate of 10 Gb/s on the copper twisted-pair.
In this thesis, an analog front-end circuit suitable for 10 GBASE-T Ethernet system has been designed and implemented using CMOS technology. The analog front-end circuit includes a baseline wander (BLW) cancellation loop, a programmable gain amplifier (PGA), a low-pass filter (LPF) and a gain amplifier. The baseline wander cancellation loop compensates the BLW by a feedback loop using a digital-to-analog converter (DAC). The programmable gain amplifier compensates the signal loss due to different channel length. The low-pass filter suppresses the alien crosstalk. The gain amplifier increases the overall gain of the entire analog front-end to satisfy the system requirement. Moreover, a frequency tuning loop which controls the frequency response of the low-pass filter is implemented in this design.
The chip is fabricated using 0.18μm 1P6M CMOS technology. According to the post-layout simulations, this AFE has gain range from 4.9dB to 13.9dB with 1.5dB gain step and 293MHz bandwidth. The chip area is 0.88 x 0.82 mm2. The power consumption is 48mW under 1.8 V supply voltage. The chip is designed and verified with post-layout simulations. Testing considerations and experimental results are also presented.
Subjects
百億位元乙太網路系統
10GBASE-T Ethernet
Type
thesis
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