High Level Synthesis of a Low-Power SOC System using GDTPOM Principle
Date Issued
2008
Date
2008
Author(s)
Chen, Ruei-Chi
Abstract
This thesis reports the Gate-level Dual-threshold Total Power Optimization Methodology (GDTPOM) to optimize 16-bits Wallace tree multiplier digital circuit. Design a low power and high speed digital circuit using 90nm MTCMOS (Multiple-Threshold voltage CMOS) standard cell library. Chapter 1 introduces CMOS development trends and the importance of power dissipation in circuit. Chapter 2 describes some algorithm which using 90nm MTCMOS standard cell library to optimize circuit. It also introduces timing models and power models of standard cell library. MTCMOS standard cell library come in fixed threshold voltage – high threshold voltage cell for low power and low threshold voltage cell for high speed. In chapter 3, we use GDTPOM to optimize multiplier digital circuit. The GDTPOM not only use static timing analysis by GDSPOM but also execute total power optimization in PrimePower tool. First the RTL design synthesis to gate-level netlist by LVT cell. Then, the gate-level netlist execute total power optimization in PrimePower tool. Finally, the gate-level netlist execute timing optimization in PrimeTime tool to meet the timing constraint. Chapter 4 is the conclusion of this research.
Subjects
MTCMOS
dual-threshold
low power
high-level synthesis
SOC
Type
thesis
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ntu-97-R95943161-1.pdf
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