Investigation of Gate Dielectrics and Carbon Interstitials on 4H-SiC MOS Capacitors
Date Issued
2014
Date
2014
Author(s)
Hsu, Chia-Ming
Abstract
In this dissertation, we have investigated different gate dielectrics on 4H-SiC, such as Al2O3, HfO2, and SiO2. At first, high-κ dielectric was deposited on SiC for MOS capacitors. The hysteresis of capacitance-voltage (C-V) curves is small and charge trapping under constant field stress is negligible. However, the leakage current is large, and the C-V shows significant C-V frequency dispersion. When the frequency increases, the measured capacitances shift downward because of border traps effect. We first proposed an equivalent circuit model including border trap effect to explain the C-V frequency dispersion on SiC. With suitable Rbt at different biases, this simulation can fit the experimental data successfully.Second, the SiO2 with different thicknesses are grown on 4H-SiC by thermal oxidation. By X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES) analysis, we first detected the C interstitials or clusters in SiC. The thick SiO2 (15.5nm) produced C interstitials in SiC.The C interstitials would trap electron during the constant field stress test. On the other hand, the thin SiO2 (7.5nm) has ideal electrical property and chemical composition, and the SiC substrate does not contain excess C in it. Moreover, we investigated different thickness of SiO2 using XPS analysis. We first depicted SiO2/4H-SiC energy band alignment of the different SiO2 thicknesses layer by layer. The Band gap (EG) and conduction band offset ( ) of SiO2 are reduced when grow thicker SiO2. The surface SiO2 layer is more perfect than the bottom layer. Nevertheless, from the XPS depth profile, both thin and thick SiO2 did not contain the silicon oxycarbides (SiCxOy) in it. From experimental result of study, the 7.5 nm SiO2is the best dielectric for SiC, which has ideal band structure and no excess C contamination.
Subjects
碳化矽
二氧化矽
碳積聚
高介電質
能帶圖
X射線光譜分析
電容電壓圖
Type
thesis
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