K-band Power Amplifier with Linearity Enhancement Techniques
Date Issued
2016
Date
2016
Author(s)
Chen, Yu-Chen
Abstract
In this thesis, two K-band power amplifiers implemented in TSMC 0.18-μm CMOS process are proposed to improve the linearity, output power, PAE and the back-off 6-dB efficiency. First, a K-band power amplifier using 1.8 V supply voltage utilizing pre-distortion parasitic diode linearizer is designed and measured. Parasitic diode linearizer is utilized to improve overall circuit linearity. With 1.4 V control voltage for the linearizer of 3-stage CS PA turned on, the measured peak small signal gain is 13.9 dB, OP1dB is 14.1 dBm, and saturation power is 15.7 dBm. The PAE has a value of 12.1% at OP1dB, and 5.2% at 6-dB back-off from P1dB. Third-order intermodulation distortion (IMD3) can be mitigated to about 18 dBc when the sweet spot appears under two-tone measurement. Second, a K-band power amplifier using optimal-selected 3 V supply voltage adopting adaptive-bias technique is designed and measured. The 2-stage cascode PA can provide higher gain and reduce matching complexity. With adaptive-bias circuit, power amplifier can be biasd at class-AB in small signal operation and class-A in large signal operation. Therefore, PAE at 6-dB back-off from P1dB can be improved, and DC power consumption can be reduced. According to the simulation results, this K-band cascade PA provides 19 dB small signal gain, OP1dB is 16.9 dBm, and PAE at OP1dB is 11.6%, PAE at 6-dB back-off from P1dB is 4.6%. Compared with the fixd-bias Class-A PA, the proposed PA saves about 30% power consumption, and the PAE at 6-dB back-off from P1dB can be improved 1.1%. According to the measurement results, large-signal performance is not as good as simulation, but 14.5% DC power consumption can be reduced by the adaptive-bias circuit. In order to meet the specification of this power amplifier, measurement results under optimized condition are provided as well. The differences between simulation and measurement of both power amplifiers are discussed including factors such as EM post-simulation, resistance selection, parasitic effect and temperature. Finally, debug results are provided.
Subjects
power amplifier
linearity
K-band
pre-distortion
parasitic diode linearizer
IMD3
back-off power-added-efficiency
optimal bias selection
adaptive-bias
Type
thesis
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