A 250MHz 4Kb SRAM Design in CMOS 0.18um Technology
Date Issued
2005
Date
2005
Author(s)
Kuo, Ming-Zhang
DOI
en-US
Abstract
Abstract
This thesis describes the implementation of a 4Kb static random access memory circuit. In order to correctly perform a read operation at low voltage, the current
latched sense amplifier is improved. This thesis is divided into five chapters. The first chapter is the introduction.
In the chapter 2, the architecture and the design considerations of SRAM are presented.
In chapter 3, we describe the sense amplifiers in detail. The difference of the
input resistance makes the delay differ a lot in sensing time.
Chapter 4 presents the circuit implementation. A 4Kb SRAM is implemented with a standard 0.18um CMOS process. The access time of SRAM is 2.0557ns. The core circuit of the chip occupies 1.056002 ╳ 1.090342 mm2 and it consumes
15.658mW when working at 250MHz.
Subjects
記憶體
SRAM
Type
thesis
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