A 50-Gb/s 10-mW analog equalizer using transformer feedback technique in 65-nm CMOS technology
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
56
Journal Issue
10
Pages
783-787
Date Issued
2009
Author(s)
Lu, Jian-Hao
Abstract
A 50-Gb/s low-power analog equalizer has been realized in 65-nm CMOS technology. This equalizer adopts the proposed transformer feedback technique to achieve a peaking gain of 18 dB at 25 GHz and low-power dissipation. The whole equalizer without the output buffer consumes 10 mW from a 1-V supply. The chip occupies 0.35 × 0.27 mm2. For a 50-Gb/s pseudorandom bit sequence of 27 - 1, the measured bit error rate is less than 10-12, and the measured maximum root-mean-square and peak-to-peak jitters are 2.7 and 12.4 ps, respectively. © 2009 IEEE.
Subjects
CMOS; Equalizer; Transformer feedback
Other Subjects
Bit error rate; CMOS integrated circuits; Feedback; Analog equalizers; CMOS technology; Low-power dissipation; Output Buffer; Peak-to-peak; Pseudo random bit sequences; Root Mean Square; Transformer feedback; Equalizers
Type
journal article
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