CMOS Oversampling Delta-Sigma Magnetic to Digital Converters
Resource
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Journal
IEEE International Symposium on Circuits and Systems, ISCAS
Pages
388-391
Date Issued
2001-05
Author(s)
Abstract
In this paper, a CMOS oversampling delta sigma (/spl Delta//spl Sigma/) magnetic to digital converter (MDC) is proposed. In the MDC, the magnetic operational amplifier (MOP) combines with the switched capacitor (SC) /spl Delta//spl Sigma/ modulator, and converts the external magnetic field into digital form. Simulation and measurement results indicate that the average digital output versus the applied magnetic field is quite linear. The prototype circuit was fabricated in a 0.5 /spl mu/m CMOS DPDM process. The circuit operates at a 5 V supply voltage and the sampling rate of 2.5 MHz. The maximum signal range of the converter is at least /spl plusmn/100 mT and the resolution can reach as small as 1 mT. The gain error within /spl plusmn/100 mT is less than 3%. The conversion gain is 1.327 mv/mT and the power consumption is 49.3 mW.
SDGs
Type
conference paper
File(s)![Thumbnail Image]()
Loading...
Name
00921874.pdf
Size
306.79 KB
Format
Adobe PDF
Checksum
(MD5):e3f8cb364ecb03fde1c568afc5474fce