Realization of array architectures for video compression algorithms
Resource
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Journal
Proceedings - IEEE International Symposium on Circuits and Systems
Journal Volume
4
Pages
1672-1675
Date Issued
1992-05
Date
1992-05
Author(s)
DOI
N/A
Abstract
In this paper, a practical design technique is presented to realize the array architecture for hierarchical block matching algorithms. A mapping procedure has been applied to derive the array processor from the algorithm. The proposed systolic array is derived to reduce the I/O bandwidth and the hardware cost. This systolic array is configurated to be single-chip or cascaded architectures to match the real-time video applications. © 2012 IEEE.
Event(s)
1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Other Subjects
Image compression; Array architecture; Block matching algorithms; Design technique; Hardware cost; Real time videos; Single chips; Video compression algorithms; Systolic arrays
Type
conference paper
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