A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme
Journal
Proceedings - IEEE International Symposium on Circuits and Systems
Journal Volume
2015-July
Pages
2393-2396
Date Issued
2015
Author(s)
Abstract
In this paper, a wide range and low power multi-rate receiver for DisplayPort Version 1.3 is proposed. In order to extend the bandwidth, a high speed AC coupled interconnect receiver comprising output compensated negative impedance and positive feedback techniques is introduced. Furthermore, the automatic bit-rate tracking scheme is used for clock and data recovery (CDR) to achieve wide data rate range. Besides, this wide range CDR is realized by omitting the power-hungry divider. Thus, the required area and the corresponding power consumption can be substantially reduced. Designed and fabricated in 90nm CMOS technology, this test chip occupies 0.23 mm 2 and consumes 90 mW. The measured root-mean-square jitter is 5.52/3.15/2.96/3.6 ps rms with the data rates of 8.1/5.4/2.7/1.62 Gb/s, respectively. The bit error rate (BER) for all data rate is less than 10 -12 for 2 7 -1 pseudo random binary sequences (PRBS).
SDGs
Type
conference paper