A Reconfigurable Decoder IC for Irregular LDPC Codes
Date Issued
2005
Date
2005
Author(s)
Jhuang, Jing-Siang
DOI
zh-TW
Abstract
In this work, we propose an architecture and implementation method of a reconfigurable decoder IC for Irregular LDPC Codes. The two most popular LDPC decoding algorithms are at probability domain and log domain. According to our system simulation, we are convinced that the LDPC code can outperform convolutional codes / Viterbi decoding algorithm. In view of saving hardware cost, we adopt log domain LDPC decoding algorithm as our target of hardware implementation.
Due to the realization of a reconfigurable decoder, different from routing-oriented dedicated decoder architecture, we adopt partially parallel and distributed computing hardware to achieve our reconfigurable and generic design concept. On the other hand, in order to increase the hardware efficiency and its throughput, we propose a permutation algorithm applied to parity-check matrix of LDPC code. Without permutation, our generic decoder will need additional 250% hardware cost, and its throughput will decrease by 50% when applied to the two IEEE communication standards, including 802.16d and 802.11n, which both support LDPC codes.
The design flow of our chip is semi-custom. That is, we use two different kinds of CAD tools, including Verilog XL and HSPICE, to do simulation / verification on digital and memory circuit respectively. We do complete Verilog system simulation to prove our architecture and circuits are correct and functional-work. In this work, our decoder can achieve 30Mbps date rate operated at clock rate of 200MHz. At the same time, it can support the LDPC parity-check matrix defined in the IEEE 802.16d and 802.11n standards.
Subjects
低密度奇偶檢查碼
可重配置解碼器
LDPC
reconfigurable
decoder
Type
thesis
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