Influence of Cell Structure and Topology on Coss of 4H-SiC MOSFET
Journal
Key Engineering Materials
Journal Volume
1057
Start Page
125
End Page
130
ISSN
10139826
Date Issued
2026
Author(s)
Abstract
This study demonstrates that the output capacitance (Coss) of a 4H-SiC MOSFET is proportional to the length of JFET (LJFET) at a low Vds, since under this condition, the gate-to-drain capacitance (Cgd) may account for nearly half of Coss. Furthermore, when Vds is low, the Coss of MOSFETs with square and hexagonal cell topologies is approximately 20% and 25% higher than that of MOSFETs with the strip cell topology, respectively, due to larger JFET areas. However, when Vds is higher, the Coss of MOSFETs with square and hexagonal cell topologies is lower because of the lower drain-to-source capacitance (Cds) resulting from smaller Pwell areas. The split-gate MOSFET can reduce Cgd, but the smaller poly-gate area decreases the depletion capability, resulting in a higher Cds. As LJFET of the MOSFET decreases, Cgd becomes lower, which may shorten the switching time, but due to the increased area of Pwell (LPW), the reverse recovery current (Irr) increases. This study proposes partially increasing the gate oxide thickness. Although this may slightly increase Cds, the shorter switching time results in a 5% reduction in the turn-on switching loss (Eon).
Subjects
Abrupt drop phenomenon
Cell topology
Output capacitance (Coss )
Split-gate MOSFET
Switching losses
Publisher
Trans Tech Publications Ltd
Type
book part