A new pipelined adaptive DFE architecture with improved convergence rate
Resource
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Journal
IEEE International Symposium on Circuits and Systems
Journal Volume
4
Pages
-
Date Issued
2002-05
Date
2002-05
Author(s)
Yang, Meng-Da
DOI
N/A
Abstract
Among existing works of high-speed pipelined adaptive decision feedback equalizer (ADFE), the pipelined ADFE using relaxed look-ahead technique results in a substantial hardware saving over the parallel processing or look-ahead approaches. However, it suffers from the SNR degradation and slow convergence rate. In this paper, a new pipelining ADFE architecture is developed. By employing the post-processing filter (PF) to cancel the most significant post-cursor inter-symbol interference (ISI) terms, the proposed ADFE architecture can help to improve the convergence rate of ADFE compared with the relaxed look-ahead ADFE architecture while at the same hardware cost. It provides an alternative approach for the design of high-seed pipelining ADFE with large speedup factor.
Type
conference paper
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