The Third-Order One-Bit Delta-Sigma Modulator for Audio Application
Date Issued
2006
Date
2006
Author(s)
Chen, Chiu-Shiung
DOI
en-US
Abstract
Abstract
The main discussion of this thesis is to design and implement the high-order one-bit delta-sigma modulator with oversampling technique applying for stereo audio system. Due to the delta-sigma modulators are insensitive to the imperfections on the analogy components such as the device mismatch and amplifier gain. And those play important parts in the analog design. Depending on the above, we can find that the delta-sigma modulators are well suitable for realization of high-resolution, accuracy and narrow band analog-to-digital (A/D) converter. The standard estimate of this modulator include: 1. Signal to noise Ratio(SNR) 2.Dynamic Range(DR)
This thesis describes that in order to achieve higher signal-to-noise ratio and lower power consumption, the SIMULINK is used to extract each influence among amplifier gain, Bandwidth and Slew Rate of the amplifier. Also, not alike before, class-AB topology are selected to be the output stage of the amplifier in order to reduce power consumption. At last, we compensate the injected charge by adding half-size dummy switches. The circuit simulation result achieves a peak signal-to-noise ratio of 88dB at a clock rate of 6.4MHz for a 25kHz signal bandwidth(OSR=128).This chip has been fabricated in a standard 0.35μm CMOS technology through CIC.
Subjects
三角積分
delta sigma
Type
thesis