Robust Test Pattern Generation for Hold-time Faults in Nanometer Technologies

Hold-time faults are gaining attention in modern technologies because of process variation, power supply noise, and temperature. Defects in FinFET technology may also casue hold-time faults. Although delay padding can eliminate above issues, the extra area and power is needed without any contribution to performance. In this thesis, a path-based hold-time fault model is proposed to cover short paths to and from every flip-flop. And the number of faults is linear to the number of flip-flops in the circuit. Two-timeframe circuit models are proposed for ATPG and fault simulation. We show that traditional path delay fault ATPG is not sufficient for hold-time faults. A hold-time fault ATPG is presented to generate robust test patterns. Experiments on large benchmark show that our test patterns are 42% shorter while 38% better in robust fault coverage than 1-detect stuck-at fault test sets. The results justify the need for hold-time fault ATPG.