The Design and Implementation of a cache within fast switch controller chip
Date Issued
2004
Date
2004
Author(s)
Chang, Shao-Feng
DOI
en-US
Abstract
In this thesis, we investigate and modify some functions within a switch controller chip. We are interested in a fast, hardware-practicable design. And our object is to speed up the switch controller chip. In our research, we focus on a commercial product, which is a switch controller chip from EZHi-Technologies, to design and to implement. The switch controller must allocate additional SRAM memory to store forwarding table and SDRAM memory as packet data buffer, but its memory system is collocated in the way of off-chip. In the situation of high data locality, the switch controller wastes much time to access the same memory data. So it becomes a fatal bottleneck with raising transmission bandwidth and port number. We implement two functions: forwarding table R/W, cache table. In order to verify lookup and update flows, we create a module named “FTAB-RW”. It exactly executes reading and writing forwarding table. For improving lookup time, we use cache table to skip some memory access. We get a good result that save 9 clocks and improve lookup time ranging from 4 to 21 clocks. And we have the worst case is as good as original design when cache missing. Besides, we do not increase update flow time overhead.
Subjects
更新
查表
交換機控制器
轉送表
快捷存取
update
lookup
switch controller
forwarding tabl
Type
thesis