Serial ATA 系統之匯流排功能性模組實作
Implementations of Bus Functional Models for the Serial ATA System
Date Issued
2005
Date
2005
Author(s)
Chen, Hung-Wen
DOI
zh-TW
Abstract
Due to the increasing complexity of modern SoC designs, verification has become one of the bottlenecks of the entire IC design process. Current verification strategy, based on traditional hardware simulation, is not able to fulfill designer’s need efficiently because of the escalating simulation time. Functional correctness is the most fundamental requirement for all hardware design. How to reduce the simulation time and increase the functional coverage are the primary issues that designers and researchers need to solve right away.
In this thesis I provide a set of Serial ATA (SATA) Bus Function Models (BFM), congruent to SATA specification. By testing design under verification (DUV) in the behavior level, simulation time can be reduced. The BFM are configurable and programmable. We could construct all topologies of the SATA system using the BFM. Clearly layered implementation, concisely programming interface and easily command sending and receiving methodologies make SATA BFM powerful in verifying a SATA DUV. SATA BFM can become a golden model, send packets to DUV, and receive packets from DUV to check if it’s functional correctly. With the self-checked test-cases provided, functional coverage increases significantly. Finally we will provide a SATA simulation environment using SATA BFM for designers to be a reference in chip or ip design.
Subjects
匯流排
驗證
Bus Functional Model
BFM
Serial ATA
Verification
Type
thesis
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