Low-voltage CMOS four-quadrant multiplier
Journal
Electronics Letters
Journal Volume
33
Journal Issue
3
Pages
207-208
Date Issued
1997-01
Date
1997-01
Author(s)
Chang, Chen-Chieh
Abstract
A new CMOS four-quadrant multiplier that can operate from supply voltages of ±1.5 V is presented. This circuit was fabricated in a standard 0.8μm single-poly double-metal CMOS process. Experimental results show that the nonlinearity can be kept <2% across the entire differential input voltage range of ±0.8V. The total harmonic distortion is <2% with the differential input range up to ±0.8V. The measured -3dB bandwidth of this multiplier is ∼5MHz. It is expected to be useful in low-voltage analogue signal-processing applications.
Subjects
Analogue multipliers; CMOS integrated circuits; Multiplying circuits
SDGs
Other Subjects
Current voltage characteristics; Electric variables measurement; Integrated circuit manufacture; MOSFET devices; Multiplying circuits; Signal processing; Time domain analysis; Analogue multipliers; Four quadrant multipliers; Total harmonic distortion; CMOS integrated circuits
Type
journal article
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