Multilayered image processing for multiscale harris corner detection in digital realization
Journal
IEEE Transactions on Industrial Electronics
Journal Volume
57
Journal Issue
5
Pages
1799-1805
Date Issued
2010
Author(s)
Abstract
The PC-based software programming used in complex or luxuriant image processing algorithms is time consuming and resource wasting. As appropriate processing for the image data indeed speedups complicated algorithms, we focus on a crucial case - multilayered processes. In this paper, we gauge deeply into the data flow of multilayered image processing to avoid waiting for the result from every previous steps to access the memory which occurs in many applicable algorithms. Based on combining the parallel and pipelined properties to eliminate unnecessary delays, we propose new visual pipeline architecture and use field programmable gate array to implement our hardware scheme. For verification, the multiscale Harris corner detector in cooperating with shape context and thin-plate splines were combined to complete our real-time experiment of the integrated hardware and software (H/S) system for pattern recognition.
Type
journal article