A 510nW 12-bit 200kS/s SAR-Assisted SAR ADC Using a Re-Switching Technique
Journal
IEEE Dig. Symp. VLSI Circuits
Pages
463-466
Date Issued
2017
Author(s)
Abstract
This paper presents a 510nW 12-bit 200kS/s SAR-assisted SAR ADC in 40nm CMOS at 0.7V supply. A re-switching technique is proposed to suppress DNL spikes so that the size of DAC capacitor array can be minimized to reduce switching energy. A set of 2-way charge pump is used to decrease settling time constant and to increase sampling linearity. The prototype ADC achieves the DNL/INL performance of 0.5/0.79 LSB. Its SNDR and SFDR at Nyquist rate are 69.1dB and 81.72dB, respectively. It results in an FoMs of 182dB and an FoM w of 1.1fJ/c.-s.
SDGs
Type
conference paper