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  3. Photonics and Optoelectronics / 光電工程學研究所
  4. Design and Implementation of Front End Circuit for Optical CDMA-Based Gigabit-EPON Receiver
 
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Design and Implementation of Front End Circuit for Optical CDMA-Based Gigabit-EPON Receiver

Date Issued
2007
Date
2007
Author(s)
Hsieh, Ming-Chih
DOI
en-US
URI
http://ntur.lib.ntu.edu.tw//handle/246246/50822
Abstract
Fiber-optic communication system is the best solution for large-capacity and low-cost communication. Recently, the data transmission has entered the gigabit domain to meet the increasing demand of the bandwidth. The backbone network and the Local-Area Network (LAN) have a great advance up to tens of gigabit per second. However, there is still a gap between backbone and LAN. The progress in access network doesn’t keep with the great advance of backbone and LAN. This is a well-known problem, “the First Mile”. A passive optical network (PON) is investigated as the best candidate for the access network, which can bridge this gap. An Optical CDMA-based EPON is a modified version of EPON, which can utilize the bandwidth better than EPON. In this work, the front end circuit of OLT receiver for Optical CDMA-based EPON system is designed and implemented. Two versions of different speed are included in this thesis. The middle-speed version operates at the rate of 1.25Gb/s. This receiver integrates the analog front end and the analog correlateor on the same chip and fabricated in the 0.35-μm CMOS process. The front end including transimpedance amplifier (TIA), variable gain amplifier (VGA) and post amplifier has a wide dynamic range to preserve the linearity of the received signal. The simulated results report the front end has the transimpedance gain of 78.7dB over the bandwidth of 1.27GHz. Under the supply voltage of 3.3V, the whole chip dissipates the power of 452mW. And the whole chip occupies the area of 1.0 × 1.4 mm2. For the high speed version, the front end circuit operates at the speed of 10Gb/s.The analog front and the analog correlator are also integrated on a single-chip but implemented in 0.18-μm CMOS technology. The analog front end is composed of TIA and two post amplifiers. For TIA, a novel topology is proposed and makes the TIA able to operate at the rate of 10Gb/s without the aid of inductor. And an inductorless circuit technique is explored and improves the bandwidth of the broadband amplifier gain cell about 25%. With the aid of novel circuit technique, the analog front end can operate at the rate of 10Gb/s without the usage of inductor, saving the whole chip area dramatically. The simulated results tell us that the analog front end has the transimpedance gain of 63dB over the bandwidth of 8.1GHz. With the 1.8V supply voltage, the whole receiver exhibits the power dissipation of 184 mW. Index Terms – Optical communication, optical receivers, optical front-end circuit, passive optical network (PON), Ethernet passive optical network (EPON), Optical CDMA, transimpedance amplifier (TIA), analog correlator.
Subjects
光纖通訊
光接收機
前端電路
被動光網路
乙太被動光網路
光分碼多工
轉阻放大器
類比相關器
Optical communication
optical receivers
optical front-end circuit
passive optical network (PON)
Ethernet passive optical network (EPON)
Optical CDMA
transimpedance amplifier (TIA)
analog correlator
Type
thesis
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