Design of Low Power SAR Analog-to-Digital Converters for Biomedical System Applications
Date Issued
2016
Date
2016
Author(s)
Jhou, Cheng-Yi
Abstract
This thesis presents two analog and mixed-signal circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the experimental prototypes, the presented techniques are verified. The first technique is the layout schemes of a unit capacitor. Compared to last work [1], the surroundings of a unit capacitor is identical to each unit capacitor, which does not take process variation into consideration. This relevant prototype SAR ADC consumes 6.2μW at 1-V supply, and the effective number of bit (ENOB) is 9.47 bits. The resultant figure of merit (FoM) is 43.7 fJ/conversion-step. The second technique is a hybrid capacitor switching procedure. In order to suppress the effect of dynamic offset in the comparator, a capacitor switching procedure is proposed. This relevant prototype SAR ADC consumes 6.0μW at 1-V supply, and the ENOB is 9.51 bits. The resultant FoM is 41.1 fJ/conversion-step. Both of the prototypes are implemented in a 0.18μm 1P6M CMOS technology.
Subjects
successive-approximation register
analog-to-digital converters
digital error correction
capacitor switching procedure
coupling
parasitic.
Type
thesis