A 15-20GHz delay-locked loop in 90nm CMOS technology
Journal
IEEE Asian Solid-State Circuits Conference (A-SSCC
Pages
213-216
Date Issued
2008-11
Author(s)
Abstract
A 15 GHz~20 GHz delay-locked loop (DLL) has been fabricated in 90 nm CMOS technology. It not only relaxes the speed requirement of the voltage-controlled delay line (VCDL), but also allows the VCDL not to operate at the highest frequency. When this DLL operates at 20 GHz, the measured root-mean-square and peak-to-peak jitters are 0.813 ps and 6.62 ps, respectively. The core area is 0.25times0.4 mm 2 and the power consumption is 49 mW for 0.9 V supply.
SDGs
Type
conference paper