Design and Implementation of CMOS Delay-Locked Loop for Interconnection Deskew
Date Issued
2006
Date
2006
Author(s)
Lin, Cheng-Kuang
DOI
en-US
Abstract
Nowadays, as the demand for high bandwidth links and high speed operation, the timing margin is shrinking. The poor performance of link will limit the data rate. How to improve the quality of transmitting and receiving data becomes an important issue. DLLs are one of the components that can be used to correct the timing skew of clock and data.
In chapter 1, the motivation of why I choose this topic to research and the applications of DLLs are described.
In chapter 2, the fundamental concepts of DLLs are introduced. The continuous-time and discrete-time models of a DLL are then presented to understand its behavior and research how its performance is affected by the system parameters.
In chapter 3, each function block of a DLL and its functions are introduced. The design issues of each circuit are described.
The entire system, each circuit block, and the simulation results are shown in chapter 4.
In chapter 5, a source-synchronous point-to-point parallel link is introduced. The DLL designed in chapter 4 is utilized for skew-compensation. The algorithm for deskew is also introduced. Chapter 6 is my conclusion.
Subjects
延遲鎖定迴路
Delay-Locked Loop
Type
thesis
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