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  4. 40-Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90nm CMOS
 
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40-Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90nm CMOS

Journal
IEEE Journal of Solid-State Circuits
Journal Volume
43
Journal Issue
3
Pages
642-655
Date Issued
2008-03
Author(s)
Chih-Fan Liao
SHEN-IUAN LIU  
DOI
10.1109/jssc.2007.916626
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/342646
https://www.scopus.com/inward/record.uri?eid=2-s2.0-40149084207&doi=10.1109%2fJSSC.2007.916626&partnerID=40&md5=42a4acd6feb436cf0db4183515d566a7
Abstract
High-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance amplifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 kΩ and a differential output swing of 520mVpp with BER < 10-9 for input spanning from 430μApp to 4mA pp. The measured integrated input-referred noise is 3.3μA rms. The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s 231 - 1 PRBS input, the recovered clock jitter is 0.7psrms and 5.6pspp. The retimed data exhibits 13.3pspp jitter with BER < 10 -9. Fabricated in 90 nm digital CMOS technology, the overall amplifier consumes 75 mW and the CDR circuit consumes 48 mW excluding the output buffers, all from a 1.2 V supply. © 2008 IEEE.
Subjects
Automatic gain controlled (AGC); Clock/data recovery (CDR); Receiver; Rotary-wave oscillator; Transimpedance amplifier
SDGs

[SDGs]SDG7

Other Subjects
CMOS integrated circuits; Electric impedance; Gain control; Jitter; Oscillators (electronic); Automatic gain controlled (AGC); Rotary wave oscillators; Transimpedance amplifiers; Power amplifiers
Type
journal article

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