Design and Implementation of Multimode Carrier Recovery Circuit for Wireless LAN
Date Issued
2004
Date
2004
Author(s)
Yang, Ya-Lan
DOI
en-US
Abstract
In this Thesis, we present a multimode carrier recovery circuit design with hardware implementation. We combine the two different Wireless LAN specifications: Bluetooth modulated in GFSK scheme and IEEE 802.11b modulated in several DPSK schemes. Using the input data mode to determine the suitable phase detector and loop filter bandwidth. We understand the bandwidth of loop filter plays an important role in this feedback loop. It dominates the loop stable time and helps the circuit to resist the channel noise. For low power consideration, gated clock is also used in this design, thus, the whole loop does not always operate on the highest frequency and the two-phase detector is not always on at the same time.
The whole loop spends about 10~35 μs to reach the stable state and meet the specification, that requires 128μs for a long preamble in IEEE 802.11b and 64μs for Bluetooth.. The power required is 2.38mW when operating in 8MHz for Bluetooth, and 11.71mW for IEEE 802.11b. The total chip has an area of 0.48*0.48mm2 and contains 14175 gates.
Subjects
頻率回復
多模組
無線區域網路
Multimode
Wireless LAN
Carrier Recovery Circuit
Type
thesis
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