Analysis and Implementation of Reconfigurable Architecture of Motion Estimation for HDTV Applications
Date Issued
2007
Date
2007
Author(s)
Tsai, Sung-Fang
DOI
en-US
Abstract
Motion estimation provides and efficient encoding tools, but it also
occupy a lot of computing power. In high definition video
application, the problem would be more serious. A reconfigurable
motion estimation with power scalability is proposed. Besides, to
support the random access requirement, a reconfigurable memory
system is also proposed. Both is successfully verified in different
two system.
With use of the video signal characteristics, based on fast search
algorithm, a parallel architecture with efficient DR techniques and
hardware-oriented algorithm is proposed. Content-adaptive
parallel-VBS fast search algorithm is firstly designed with the
inter-/intra-candidate DR capability in hardware, and computational
complexity can be largely saved. It provides controllability on
computation so as to achieve power scalability. It reduce
computation with graceful coding performance degradation through
content adaptation.
On the motion estimation architecture, based on the systolic array
and 2-D adder tree architecture, 4 direction of movement is
supported. It enables the support of irregular moving path of fast
algorithm efficiently. Advanced searching flow are applied to
support inter-candidate DR and to reduce the latency cycles.
IME require 2D parallel access on SW memory. Traditional memory
organization cannot provide the required parallel access. A
reconfigurable memory system design is proposed. It allows various
reconfigurable engines and dedicated accelerators with various
access patterns to access data through run-time configurable memory
system. The reconfigurable memory system contains three hierarchies,
block translation cache, reconfgurable datapath, and physical
memories. The reconfigurable datapath allows arbitrary parallel 2D
access patterns including row, column, block, and subsampling by
run-time reconfigurations. The block translation cache uses one tag
entry to represent a block of pixels in a frame.
In chip implementation, proposed reconfigurable IME uses TSMC 0.18
μm CMOS 1P6M process. According to chip measurement result, it
may support from QCIF with 0.24mW up to HDTV1920p with 49.86mW.
In system implementation, it has verified in low-power and
power-aware H.264 encoder, fabricated with TSMC 0.18 μm CMOS
1P6M process. Final power consumption is 2.8mW ~67.2mW. In this
different system, proposed reconfigurable motion estimation and
reconfigurable memory provide proper power and quality tradeoff.
Proposed architecture is very suitable for mobile application with
high definition video requirement.
Subjects
移動估計
視訊編碼
可重組架構
功率可調系統
Motion Estimation
Video Coding
Reconfigurable Architecture
Power aware system
HDTV
Type
thesis
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