子計劃六：可重組化運算之測試設計(I)
Date Issued
2003-07-31
Date
2003-07-31
Author(s)
DOI
912215E002040
Abstract
Microprocessors plan a very important role in the modern microelectronics industry. In
addition to serving as the central processing unit (CPU) in desktop computers, notebooks, or
workstations, microprocessors are often utilized as the main control unit of many electronics
products. Since the introduction of Intel 4004, microprocessors have advanced substantially in
terms of the chip area, performance, and circuit/functionality complexity. All these
improvements pose severe challenges on not only design verification, but also manufacturing
testing.
The purpose of this project is to develop microprocessor manufacturing techniques which
can achieve the desired structural fault coverage without or with the least amount of DfT
(Design-for-Test) circuitry. The main results of the first year include (1) collecting and studying
microprocessor testing related papers and research results, (2) development of test program for
the Parwan Processor and achieve acceptable structural fault coverage, and (3) collecting and
analyzing publicly available processor cores for further research and study.
Subjects
microprocessor
self-testing
structural faults
Publisher
臺北市：國立臺灣大學電子工程學研究所
Type
report
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