Abstraction Techniques for Design Depipelining
Date Issued
2014
Date
2014
Author(s)
Huang, Mao-Kai
Abstract
For simulation-based verification, control circuits for synchronization in pipelined design are tedious, especially for the event-driven simulation. Therefore, depipelining technique plays an important role in the control logic simplification of pipelined design. However, it would cause state explosion due to the need of formulating the implementation with respect to a certain specification or property. Consequently, it is not scalable for current superscalar RTL design. To conquer these problems, the techniques utilizing various strategies such as decomposition and abstraction might be the solutions. The abstraction technique that maps concrete paths to abstract ones attempts to reduce the number of states. Therefore, we propose a design depipelining algorithm which computes approximate abstraction of pipelined design. Moreover, a netlist will be generated in our approach. Although the throughput of the netlist is different from the original design, we ensure that the simulation outputs of these two designs are identical. In addition, to enhance the efficiency, finite-state machine extraction and abstraction techniques are applied to our work. The experimental results show that our algorithm is effective in increasing simulation-speed of pipelined design. When compared to the loop-unrolling technique, the simulation of our work is much faster.
Subjects
抽象化技術
去管道化
模擬
驗證
Type
thesis
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